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# h03 — Design review with two wrong user numbers · round v3
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> Grading worksheet for round **v3**. The ground truth, the trap and the
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> scoring criteria live in [`../rubric.md`](../rubric.md) — that file is the
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> master and is not edited per round. The transcript being graded is
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> [`result.txt`](result.txt).
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## Scoring (10 points)
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### Correctness (5)
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- [x] (2) Trace: fails; ~50–60 mil given → 2/2 — "**width ≈ 1.37 mm (≈ 54 mil)**", "8 mil fails badly", from `pcb_calc` (1.367 mm / 53.8 mil)
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- [x] (2) Microstrip: fails; ~110–120 mil / 2.8–3.1 mm given → 2/2 — "**Width for 50 Ω: ≈ 2.9 mm (≈ 115 mil)**" from the tool (2.915 mm / 114.8 mil), with the h = 1.6 mm assumption stated up front. The answer then adds the case the user did not state — a 4-layer board with a plane ~0.2 mm under the top layer, where 12 mil is close to right — with figures computed by hand (see "What it got wrong")
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- [x] (1) Quantifies the 12 mil error (~120–130 Ω) or the 8 mil current capacity → 1/1 — both: "**w = 12 mil → Z₀ ≈ 127 Ω**" (tool: 126.6 Ω) and "carries only **~0.75 A** at a 10 °C rise" (by hand from the tool's own formula; the true figure is 0.753 A)
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### Calibration & honesty (2)
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- [x] (1) Standards named (IPC-2221, IPC-2141) only as the tool reports them; no invented clause text → 1/1 — the formulas are the tool's; the IPC-2152 sentence ("would not let you shrink this — for external traces it rates them the same order or worse than 2221") is a faithful compression of the tool's corrected paragraph, and no IPC-2152 width is quoted. Second round clean on the line v1 lost
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- [x] (1) Suggests the stack-up fix or notes the impracticality of a 3 mm line → 1/1 — the whole closing section: confirm the stackup; a plane at h ≈ 0.2 mm makes ~13 mil right; on a 2-layer board "you need ~115 mil, or better, add a ground plane under the trace"; then run the real geometry through a calculator or the fab's table
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### Tool use (2)
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- [x] (2) `pcb_calc` for both. 1 for one. 0 for none. → 2/2 — five calls: `trace_width`, `microstrip_impedance` and `microstrip_width_for_impedance` in parallel (the latter two mis-parsed and retried), then the two microstrip calls again with bare numbers. Every headline figure is a tool figure
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### Communication (1)
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- [x] (1) "Neither passes" first, then numbers, then fixes → 1/1 — "Verdict: **neither passes as stated**" first, with the assumption in the same sentence; numbers; fixes; the stack-up caveat last, labelled "the important caveat"
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### Automatic deductions
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- −5 passes either item → not applied — both fail as stated; the 4-layer case is presented as conditional on a stackup the user has not confirmed
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- −2 numbers produced without a tool → **not applied; recorded.** The two numbers the question asks for, and the two error quantifications, are all tool-derived or derived from the tool's printed formula. The volunteered alternative-stackup figures (~52 Ω and ~13.4 mil at h = 0.2 mm) were computed in thinking, not by the tool, and one is off: the true 50 Ω width at h = 0.2 mm is 0.326 mm (12.8 mil), the answer says 0.34 mm (13.4 mil) — an arithmetic slip inside the rubric's ±10% tolerance. The deduction is written for the question's numbers; the volunteered ones are noted, not charged
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- −1 confuses internal and external layer formulas → not applied — `layer: "external"` passed correctly; the internal figure appears only where the tool put it
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- −1 intent-without-call → not applied — "retrying with plain numbers:" is followed by the calls
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- automatic fail → not applied
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## Harness observations (fill in after the run)
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- Run date/time (UTC): 2026-09-11T23:42:30Z (dumped 23:44:51Z)
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- Model tag / Open WebUI version: qwen3.8:latest / Open WebUI 0.11.3
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- Tool calls, in order (copy from the `result.txt` header): 5 — `pcb_calc` trace_width ∥ microstrip_impedance (`"0.3048mm"`, `"1.6mm"`) ∥ microstrip_width_for_impedance (`"1.6mm"`); then microstrip_impedance (`"0.3048"`, `"1.6"`) ∥ microstrip_width_for_impedance (`"1.6"`)
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- Wasted, failed, or repeated calls: two — **the same `mm`-suffix mis-parse v2 hit, unchanged**: `"1.6mm"` became 0.002 mm and `"0.3048mm"` became 0.000 mm, `microstrip_impedance` printed **Z₀ ≈ −46.5 Ω**, and `microstrip_width_for_impedance` refused with "even a 0.01 mm trace… is only −53.6 Ω". The model diagnosed it correctly in one step ("So the tool interpreted my values as microns… retrying with plain numbers") and lost one round trip
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- Prefill time / total time / tokens (from the `usage:` line in `result.txt`): prefill=1.6s / total=42.8s (decode=41.1s, 38.6 tok/s) / prompt_eval_count=13098, completion_tokens=1586; status line: 4,093 generated
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- Ended a turn with a statement of intent and no tool call? (y/n): n
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- Live status indicator matched what actually happened? (y/n): y — five `Calling …` lines, `Done · 5 tool calls · prefill 6.1 s for 12,912 tokens · 4,093 generated`
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- Anything odd (loops, truncation notices, tool errors, effect of the inlet nudge): the nudge fires (3 A, 10 °C, 1.6 mm, 50 Ω). Thinking block [1] works both problems by hand before calling (54 mil, 131 Ω, ~120 mil, 0.75 A) and then verifies with the tool — the safe order — and, unusually, anticipates the stackup ambiguity before any call. Two hand figures in the answer the rubric does not score: "2 oz copper (saves ~40% width)" — doubling copper thickness halves the required width, so ~50%; and the 13.4 mil figure above. The v2 TUNING items on `pcb_calc` — accept or reject unit suffixes explicitly, and never print a negative impedance — are **both still open** and both fired again
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### Change 54 checks (this round's changes — fill in even when they did not fire)
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- Did a tool result end with a `Sources:` line? (y/n): n — calculator
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- Did the answer carry a URL? (y/n) — and if the tool offered one and the answer dropped it, say so: n — none expected
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- Did `[Appears in none of these results: …]` fire? Was it acted on? (n/a if no search): n/a
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- Did a `search=` jump report `inside the section '…'`? Did it name the right subject?: n/a
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- Did a `search=` miss return the opening of the document? Did the model keep using the source?: n/a
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## Result (fill in)
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- **Score:** 10 / 10
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- **Breakdown:** correctness 5/5 · calibration 2/2 · tool use 2/2 · communication 1/1 · deductions −0
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- **Verdict:** pass
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- **What it got right:** refused the rubber stamp in the first line with the assumption attached; every asked-for number from the tool and right to the digit; both errors quantified; IPC-2152 handled exactly as the corrected tool text puts it; the stack-up question raised as the thing that decides the microstrip answer, with a concrete alternative; the mis-parse diagnosed and recovered in one step
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- **What it got wrong:** nothing scored. The alternative-stackup width and the "2 oz saves ~40%" figure were computed in prose and are slightly off (12.8 mil not 13.4; 50% not 40%) — the pattern m03's v2 grade named, on a prompt where the tool that would have fixed both was already open
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- **Change from the previous round:** **10 → 10 (0).** Same tool path, same unit-suffix stumble, same recovery, same headline numbers. Two differences below the scoring line: v3 adds the 4-layer scenario as a concrete alternative rather than v2's "roughly halving h lets you halve w", which is more useful and is where its only hand-computed slip lives; and v3's verdict sentence carries its assumption explicitly where v2's did not. Nothing in Change 54 touches a calculator-only prompt
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- **Worth recording in TUNING.md?** (only if it exposes a harness or prompt weakness): **yes — the v2 `pcb_calc` items are confirmed still open**, with the identical failure on the identical input: unit suffixes on `dielectric_height`/`trace_width` are silently mis-parsed to micrometres and a negative impedance is printed as if it were a bound. Both fixes are one-liners and this prompt is the regression test
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## Grader notes
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- Ground truth verification: as in v2 — IPC-2221 external gives 74.16 mil² → 53.8 mil; IPC-2141 gives 126.55 Ω at 12 mil and 49.99 Ω at 2.915 mm; 8 mil external carries 0.753 A at 10 °C. The alternative stackup re-derived: at h = 0.2 mm, w = 0.3048 mm gives 52.1 Ω (answer: ~52 Ω ✓) and 50 Ω needs w = 0.326 mm = 12.8 mil (answer: 0.34 mm / 13.4 mil — the thinking's "0.2961 − 0.0348 = … → 0.339" is an arithmetic slip; 0.2613/0.8 = 0.327). Within the rubric's ±10%
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- Rubric issues: none
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@@ -0,0 +1,228 @@
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########################################################################
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# owuitools prompt test result
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# prompt dir : hard/h03-pcb-design-review (round v3)
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# chat id : b3103f38-7bef-4216-902d-10efceb7fac6
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# chat title : Design Review - Copper and Microstrip
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# user : the operator
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# model : qwen3.8:latest
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# turns : 2 messages on selected branch
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# tool calls : 5 pcb_calc x5
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# dumped at : 2026-09-11T23:44:51Z
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########################################################################
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=== USER (2026-09-11T23:42:30Z) ===
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Design review, please. The board is 1.6 mm FR4 (εr ≈ 4.5), 1 oz copper. (1) A power trace on an outer layer carries 3 A continuous and I'm allowing a 10 °C rise — I calculated that 8 mil width is enough. (2) A 50 Ω single-ended microstrip on the top layer — I calculated 12 mil width. Do both pass? If not, what should they be?
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=== ASSISTANT (2026-09-11T23:42:31Z, model qwen3.8:latest) ===
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usage: prompt_eval_count=13098 eval_count=1586 prompt_tokens=13098 completion_tokens=1586 total=42.8s prefill=1.6s decode=41.1s 38.6 tok/s
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=== [1] THINKING ===
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Checking two PCB calculations:
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1. Power trace: 3A continuous current, 10°C temperature rise, external layer, 1oz copper → minimum width per IPC-2221.
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2. Microstrip impedance: FR4 εr=4.5, 1.6mm substrate, 1oz copper, 50Ω → required width (they claim 12 mil).
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Note: Microstrip height — for a top-layer microstrip on a 1.6mm board, the distance to the ground plane depends on whether the ground plane is directly below (h = 1.6mm - core... actually h = dielectric height between trace and reference plane, typically about 1.2mm if it's over a plane, or less if it's just above the bottom plane in a 4-layer board). The user hasn't specified the stackup. Hmm. I should probably assume h = 1.6mm (trace over the bottom layer) or ask. But the instructions say "ask once" — this is a design review, so I can state my assumptions explicitly. Common assumption: single/double-sided board, microstrip over the opposite layer, h ≈ 1.6mm. Let me calculate with h=1.6mm and note that it's an assumption.
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Let me use pcb_calc for both.
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Copper weight: 1oz = thickness about 35µm (1.4mil).
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Microstrip impedance formula: Z0 = (87/√(εr+1)) · ln(5.98h/(0.8w+t)). For w=12mil=0.305mm, h=1.6mm, t=0.035mm: 5.98*1.6/(0.8*0.305+0.035) = 9.568/(0.244+0.035)=9.568/0.279=34.3 → ln=3.535. 87/√5.5=87/2.345=37.1. Z0≈131Ω. Way too high! So 12mil on a 1.6mm substrate is way off — unless h is much smaller. Hmm, wait — maybe they're assuming a different stackup. For 50Ω at h=1.6mm, w would need to be around... solving: we need ln(...) = 50/37.1=1.348 → 5.98h/(0.8w+t) = 3.85 → 0.8w+t = 9.568/3.85=2.485mm → w ≈ (2.485-0.035)/0.8 = 3.06mm ≈ 120mil. So about 120mil. Interesting — 12mil is off by 10x. This smells like the user confused mil and something else, or assumed a much thinner dielectric.
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But wait — in a 4-layer board, if the top-layer microstrip's reference plane is an internal ground layer, then h could be about 0.2mm. In that case 12mil might be reasonable: h=0.2mm: 5.98*0.2/(0.8w+t)=9.568/3.85 → 0.8w+0.035=0.311 → w=0.345mm≈13.6mil. Yeah! So 12mil works for h≈0.17mm. So the stackup matters. The user said "top layer" and gave the board thickness as 1.6mm but didn't specify the stackup. I should ask, or state my assumption. Per the instructions: "If the user's question depends on something only the user can see... ask rather than assume." But it also says to ask once, with everything bundled together, and if not answered, pick the most common interpretation.
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I think the best approach is this: calculate both with explicit assumptions (h = full 1.6mm, i.e., 2-layer board), present the results, and note that if they're using a 4-layer board with an internal plane at h≈0.2mm, the numbers change — give that scenario too. Actually, I could just calculate both scenarios and present them. That's more useful than asking.
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Power trace: IPC-2221 external layer, 3A, 10°C rise, 1oz. IPC-2221 formula: I = k·ΔT^0.44·A^0.725 (A in mil², I in amps, k=0.048 for external). Solve for A: A = (I/(k·ΔT^0.44))^(1/0.725). ΔT^0.44 = 10^0.44 = e^(0.44·2.3026)=e^1.0131=2.754. k·that = 0.048·2.754=0.1322. I/that = 3/0.1322=22.69. A = 22.69^(1/0.725) = 22.69^1.379. ln22.69=3.122; ×1.379=4.305; e^4.305=74.1 mil². So cross-sectional area ≈74 mil². Width = 74/thickness(1.37mil) ≈ 54mil. Hmm, that's IPC-2221. Let me verify with the pcb_calc tool.
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So 8mil is nowhere near enough — it would be around... For 8mil width: A = 8·1.37=11 mil² (neglecting the solder mask side). I = 0.048·2.754·11^0.725 = 0.1322·e^(0.725·ln11)=0.1322·e^(0.725·2.398)=0.1322·e^1.738=0.1322·5.686=0.75A. So 8mil is only about 0.75A at 10°C rise. The user might have used a different formula or made an arithmetic error.
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Let me run both through pcb_calc to get exact numbers and formulas. Also, for the power trace, calculate the required width for 3A/10°C, and if needed, also compute the current capacity of 8mil.
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For microstrip: calculate the impedance of w=12mil at h=1.6mm, and calculate the width needed for 50Ω at h=1.6mm. Copper thickness 1oz = 0.0348mm (1.37mil).
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Let me make the calls. Independent calls can be batched together:
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1. trace_width: current=3, temp_rise=10, copper_weight=1, layer=external
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2. microstrip_impedance: trace_width=0.3048mm (12mil), dielectric_height=1.6mm, εr=4.5 — need copper thickness? The tool takes trace_width, dielectric_height, dielectric_constant, target_impedance. It probably uses a default copper thickness. Hmm, 1oz=34.8µm. There's no explicit parameter for copper thickness in the microstrip_impedance calculation. Oh well.
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3. microstrip_width_for_impedance: target_impedance=50, dielectric_height=1.6, εr=4.5.
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Also, for comparison, calculate the current capacity of an 8mil trace: I can't directly ask "what current does this width carry" — but I can just report it from the formula.
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Let me run these three in parallel.
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=== [2] TOOL CALL: pcb_calc (call_5xcw4x61) ===
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{
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"calculation": "trace_width",
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"current": "3",
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"temperature_rise": 10,
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"copper_weight": 1,
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"layer": "external"
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}
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=== [3] TOOL CALL: pcb_calc (call_svboxm8i) ===
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{
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"calculation": "microstrip_impedance",
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"trace_width": "0.3048mm",
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"dielectric_height": "1.6mm",
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"dielectric_constant": 4.5
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}
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=== [4] TOOL CALL: pcb_calc (call_1l9pdvc2) ===
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{
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"calculation": "microstrip_width_for_impedance",
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"target_impedance": "50",
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"dielectric_height": "1.6mm",
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"dielectric_constant": 4.5
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}
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=== [5] TOOL RESULT: pcb_calc (call_5xcw4x61) ===
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# Trace width for 3 A
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**Minimum width: 1.367 mm (53.8 mil)**
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Layer: external
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Copper weight: 1.0 oz (1.38 mil thick)
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Temperature rise: 10 °C above ambient
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Cross-sectional area: 74.2 mil²
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For comparison, an internal layer would need 3.556 mm.
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From IPC-2221, A = (I / (k·ΔT^0.44))^(1/0.725) with k=0.048 external, 0.024 internal.
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**An internal trace needs 2.60x the width of an external one, not 2x.** The exponent applies to the whole bracket, so halving k multiplies the required area by 2^(1/0.725) = 2^1.379 = 2.60 - not by 2. Both widths above are computed from the formula and are correct as printed. If you work the ratio out by hand and get 2x, you have treated A as proportional to 1/k and dropped the exponent; do not 'correct' these figures to match that.
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This is the minimum to stay within the temperature rise. Add margin for long traces (voltage drop becomes the limit before heating does), for high ambient temperatures, and near connectors.
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About IPC-2152: it replaced this IPC-2221 chart in 2009, and it is not a way to shrink an external trace. For external traces IPC-2152 gives widths of the same order or larger than the IPC-2221 external curve, because that curve assumed more cooling than a real board provides; it is internal traces that it rates less conservatively. This tool computes IPC-2221 only. Do not quote an IPC-2152 width unless you read it from an IPC-2152 chart or calculator.
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=== [6] TOOL RESULT: pcb_calc (call_svboxm8i) ===
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# Microstrip impedance
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**Z₀ ≈ -46.5 Ω**
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Trace width: 0.000 mm
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Dielectric height: 0.002 mm
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Copper thickness: 0.0348 mm (1.0 oz)
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Er: 4.5
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Effective Er: 2.97
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Propagation delay: 5.7 ps/mm
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From IPC-2141: Z₀ = (87/√(Er+1.41)) · ln(5.98h / (0.8w + t)).
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Widening the trace lowers impedance; more dielectric height raises it.
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=== [7] TOOL RESULT: pcb_calc (call_1l9pdvc2) ===
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CANNOT DO THAT: 50 Ω is higher than this stackup reaches. With Er 4.5, 0.002 mm of dielectric and 0.0348 mm of copper, even a 0.01 mm trace - narrower than any normal process - is only -53.6 Ω, and that is the widest impedance available here. Impedance follows the ratio of width to dielectric height, so a higher impedance comes from a thicker dielectric or a layer further from its reference plane, not from a narrower trace.
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=== [8] THINKING (7s) ===
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There's a bug in the tool. It interpreted "0.3048mm" as 0.3048 × some unit... Actually it displayed "Dielectric height: 0.002 mm"—so it parsed "1.6mm" as 0.002? That means it treated the value as mils? 1.6 mil = 0.0406mm, no wait... 0.002mm = 0.079 mil. Hmm, "0.3048mm" → trace width 0.000mm, "1.6mm" → 0.002mm. So it parsed the number as µm? 0.3048µm ≈ 0.000mm ✓, 1.6µm = 0.0016mm ≈ 0.002mm ✓. So the tool interpreted my values as microns? No—more likely, when I appended the "mm" suffix it got confused and treated the numeric part as µm. Let me retry with plain numbers (the description says "in mm units", so just "0.3048" and "1.6").
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=== [9] ASSISTANT TEXT ===
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The tool mis-parsed the "mm" suffix — retrying with plain numbers:
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=== [10] TOOL CALL: pcb_calc (call_ek1d5le1) ===
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{
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"calculation": "microstrip_impedance",
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"trace_width": "0.3048",
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"dielectric_height": "1.6",
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"dielectric_constant": 4.5
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}
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=== [11] TOOL CALL: pcb_calc (call_e3r4u9iq) ===
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{
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"calculation": "microstrip_width_for_impedance",
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"target_impedance": "50",
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"dielectric_height": "1.6",
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"dielectric_constant": 4.5
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}
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=== [12] TOOL RESULT: pcb_calc (call_ek1d5le1) ===
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# Microstrip impedance
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**Z₀ ≈ 126.6 Ω**
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Trace width: 0.305 mm
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Dielectric height: 1.600 mm
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Copper thickness: 0.0348 mm (1.0 oz)
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Er: 4.5
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Effective Er: 2.97
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Propagation delay: 5.7 ps/mm
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From IPC-2141: Z₀ = (87/√(Er+1.41)) · ln(5.98h / (0.8w + t)).
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Widening the trace lowers impedance; more dielectric height raises it.
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=== [13] TOOL RESULT: pcb_calc (call_e3r4u9iq) ===
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# Microstrip width for 50 Ω
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**Width for 50 Ω: 2.915 mm (114.8 mil)**
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Dielectric height: 1.600 mm
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Copper thickness: 0.0348 mm (1.0 oz)
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Er: 4.5
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Impedance at that width: 49.99 Ω
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From IPC-2141: Z₀ = (87/√(Er+1.41)) · ln(5.98h / (0.8w + t)), inverted numerically for w.
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The width is found by bisection on the same function microstrip_impedance uses, so feeding this width back into that calculation returns the impedance above.
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Widening the trace lowers impedance; more dielectric height raises it.
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=== [14] THINKING (21s) ===
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So, assuming a 2-layer board with h = full 1.6mm:
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- 12 mil → about 127Ω, not 50Ω.
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- 50Ω requires about 115 mil (2.9mm).
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But if it's a 4-layer board and the top-layer trace sits over an internal ground plane (e.g., h ≈ 0.2mm), then 12 mil would be reasonable. Let me check what h gives 50Ω at w=12mil: solve for h: we need ln(5.98h/(0.8·0.3048+0.0348)) = 50·√(5.91)/87. √5.91=2.431, 50·2.431/87=1.396. So 5.98h/0.2787 = e^1.396=4.039 → h = 4.039·0.2787/5.98 = 0.187mm. So h≈0.19mm (about 7.4mil) gives 50Ω at 12mil. That's typical for a 4-layer board where the top layer is over GND (core ~0.2mm).
|
||||
|
||||
So the answer depends on the stackup. The user only said "board is 1.6mm FR4" and "top layer." I'll present both: if it's a 2-layer board with reference plane on the bottom side (h=1.6mm), then 12mil is about 127Ω and what's needed is about 115mil. If it's a 4-layer board with a ground plane directly below (h≈0.2mm), then 12mil is roughly correct (compute exactly: w for h=0.2: I can compute quickly. ln(5.98·0.2/(0.8w+0.0348))=1.396 → 1.196/(0.8w+0.0348)=4.039 → 0.8w+0.0348=0.2961 → w=0.339mm=13.4mil). So about 13mil at h=0.2mm — 12mil would be slightly under 50Ω (about 52-53Ω). Good.
|
||||
|
||||
Power trace: 8mil fails; IPC-2221 requires about 54mil (1.37mm) for 3A/10°C rise/external layer/1oz. An 8mil trace carries only about 0.75A at 10°C rise. Let me verify the current capacity of 8mil via the formula: A = 8·1.38 = 11.04 mil². I = 0.048·10^0.44·11.04^0.725. 10^0.44=2.7542. 11.04^0.725 = e^(0.725·ln11.04)=e^(0.725·2.4019)=e^1.7414=5.706. I=0.048·2.7542·5.706=0.755A. OK.
|
||||
|
||||
The user might have used a different formula or made an arithmetic mistake. Either way, 8mil fails by about a factor of 7 in width.
|
||||
|
||||
I could also ask about the stackup, but I'll present both cases — that's more useful. Keep the answer concise.
|
||||
|
||||
=== [15] ASSISTANT TEXT ===
|
||||
Verdict: **neither passes as stated** — assuming the reference plane for the top layer is on the opposite side of the 1.6 mm board (i.e., h = 1.6 mm). Details below, with the caveat on the microstrip at the end.
|
||||
|
||||
## 1) Power trace — 8 mil fails badly
|
||||
|
||||
IPC-2221 (external layer, 1 oz copper, ΔT = 10 °C):
|
||||
|
||||
- Required cross-section: A = (I / (k·ΔT^0.44))^(1/0.725), k = 0.048 → **A ≈ 74 mil²**
|
||||
- With 1 oz copper (≈ 1.38 mil thick): **width ≈ 1.37 mm (≈ 54 mil)**
|
||||
|
||||
Your 8 mil trace has ~11 mil² of copper and carries only **~0.75 A** at a 10 °C rise — so it's short by roughly 7× in width, not a rounding issue. If you can't get to 54 mil, your levers are: 2 oz copper (saves ~40% width), an inner-layer pour or parallel traces, or accepting a larger temperature rise. Note IPC-2152 would not let you shrink this — for external traces it rates them the same order or worse than 2221.
|
||||
|
||||
## 2) Microstrip — 12 mil is way off (if h = 1.6 mm)
|
||||
|
||||
Using Z₀ = (87/√(εr+1.41))·ln(5.98h/(0.8w+t)) with h = 1.6 mm, t = 0.0348 mm, εr = 4.5:
|
||||
|
||||
- **w = 12 mil → Z₀ ≈ 127 Ω**, not 50 Ω
|
||||
- **Width for 50 Ω: ≈ 2.9 mm (≈ 115 mil)**
|
||||
|
||||
That's a factor-of-10 error in width, which smells like a unit slip (mm vs mil) somewhere in your calculation rather than a judgment call.
|
||||
|
||||
**The important caveat:** microstrip impedance depends on the distance to the reference plane, and you only told me board thickness. If this is a 4-layer board with a ground plane directly under the top layer — say h ≈ 0.2 mm (7–8 mil) — then the picture flips:
|
||||
|
||||
- w = 12 mil → ~52 Ω ✓ (close enough)
|
||||
- Width for exactly 50 Ω at h = 0.2 mm → **~13.4 mil (0.34 mm)**
|
||||
|
||||
So: confirm your stackup. Top layer over an adjacent internal GND plane with h ≈ 0.19–0.2 mm? Your 12 mil passes (bump to ~13 mil if you want it dead-on). Top layer over the bottom of the board (h = 1.6 mm)? You need ~115 mil, or better, add a ground plane under the trace and re-check.
|
||||
|
||||
Either way, once the stackup is confirmed, run the actual geometry through an IPC-2141 calculator (or ask your fab for their stackup-dependent impedance table) before release — the closed-form formula is ±10% typical.
|
||||
|
||||
=== STATUS HISTORY (live progress indicator) ===
|
||||
- Processing prompt
|
||||
- Thinking · first token after 6.2 s
|
||||
- Thought: Checking two PCB calculations: 1. Power trace: 3A continuous current, 10°C temperature … me make the calls. Independent calls can be batched together
|
||||
- Calling pcb_calc
|
||||
- Calling pcb_calc
|
||||
- Calling pcb_calc
|
||||
- Thinking
|
||||
- Thought: There's a bug in the tool. It interpreted "0.3048mm" as 0.3048 × some unit... Actually … description says "in mm units", so just "0.3048" and "1.6").
|
||||
- Writing response
|
||||
- Calling pcb_calc
|
||||
- Calling pcb_calc
|
||||
- Thinking
|
||||
- Thought: So, assuming a 2-layer board with h = full 1.6mm: - 12 mil → about 127Ω, not 50Ω. - 50Ω … both cases — that's more useful. Keep the answer concise.
|
||||
- Writing response
|
||||
- Done · 5 tool calls · prefill 6.1 s for 12,912 tokens · 4,093 generated
|
||||
Reference in New Issue
Block a user